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| Freescale Semiconductor Product Preview Document Number: MC1322x Rev. 1.7 06/2008 MC13224V MC13224V Advanced ZigBeeTM- Compliant Platform-in-Package (PiP) for the 2.4 GHz IEEE(R) 802.15.4 Standard 1 Introduction Device MC13224V 1 Package Information Case 1901-01 99-Pin [9.5X9.5X1.2mm] Ordering Information Device Marking 1 Package LGA LGA 13224V 13224V MC13224VR21 See Table 1 for more details. Contents 1 2 3 4 5 6 7 8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MCU Peripherals . . . . . . . . . . . . . . . . . . . . . . 15 Pin Assignments and Connections . . . . . . 24 System Electrical Specification . . . . . . . . . 32 Developer Environment . . . . . . . . . . . . . . . . 44 Preliminary Mechanical Diagrams (Case 1901-01, non-JEDEC) . . . . . . . . . . . . 46 The MC13224V is Freescale's third-generation ZigBee platform which incorporate a complete, low power, 2.4 GHz radio frequency transceiver, 32-bit ARM7 core based MCU, hardware acceleration for both the IEEE 802.15.4 MAC and AES security, and a full set of MCU peripherals into a 99-pin LGA Platform-in-Package (PiP). The MC13224V solution can be used for wireless applications ranging from simple proprietary point-to-point connectivity to complete ZigBee mesh networking. The MC13224V is designed to provide a highly integrated, total solution, with premier processing capabilities and very low power consumption. The MC13224V MCU resources offer superior processing power for ZigBee applications. A full 32-bit ARM7TDMI-S core operates up to 26 MHz. A 128 Kbyte FLASH memory is mirrored into a 96 Kbyte RAM for upper stack and applications software. In addition, an 80 Kbyte ROM is available for boot software, standardized IEEE 802.15.4 MAC and This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved. communications stack software. A full set of peripherals and Direct Memory Access (DMA) capability for transceiver packet data complement the processor core. The RF radio interface provides for low cost and the high density as shown in Figure 1. An onboard balun along with a TX/RX switch allows direct connection to a single-ended 50- antenna. The integrated PA provides programmable output power typically from -30 dBm to +4 dBm, and the RX LNA provides -95 dBm sensitivity. In addition, separate complementary PA outputs allow use of an external PA and/or an external LNA for extended range applications. The device also has onboard bypass capacitors and crystal load capacitors for the smallest footprint in the industry. All components are integrated into the package except the crystal and antenna. PA RF TX/RX SWITCH LNA ANALOG TRANSMITTER BALUN ANALOG RECEIVER Figure 1. MC13224V RF Radio Interface In addition to the best-in-class MCU performance and power, the MC13224V also provides best-in-class power savings. Typical transmit or receive current is 20 mA with the CPU at 2 MHz operation and even lower with the bus stealing enabled. Onboard power supply regulation is provided for source voltages from 2.0 Vdc to 3.6 Vdc, and the source voltage can be as low as a regulated 1.8 Vdc if the non-volatile memory is powered directly from the source. Numerous low current modes are available to maximize battery life including sleep or restricted performance operation. Applications include, but are not limited to, the following: * Residential and commercial automation -- Lighting control -- Security -- Access control -- Heating, ventilation, air-conditioning (HVAC) -- Automated meter reading (AMR) * Industrial Control MC13224V Product Preview, Rev. 1.7 2 Freescale Semiconductor * * -- Asset tracking and monitoring -- Homeland security -- Process management -- Environmental monitoring and control -- HVAC -- Automated meter reading Health Care -- Patient monitoring -- Fitness monitoring Consumer -- Remote control -- Entertainment systems -- Cellular phone attach 1.1 Ordering Information Table 1. Orderable Parts Details Table 1 provides additional details about the MC13224V Device Operating Temp Range (TA.) -40 to 105 C LGA Package Memory Options Description MC13224V MC13224VR2 -40 to 105 C LGA Tape and Reel 96KB RAM, Intended for 802.15.4 Standard compliant applications, 128KB Flash Freescale 802.15.4 MAC, and Freescale BeeStack. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 3 2 2.1 Features Block Diagram 24 MHz (typ) 32.768 KHz (optional) This section provides a simplified block diagram and highlights MC13224V features. Figure 2 shows a simplified block diagram of the MC13224V. BATTERY DETECT RF OSCILLATOR & CLOCK GENERATION RADIO INTERFACE MODULE (RIF) DIGITAL MODEM TX MODEM RX MODEM 802.15.4 MAC ACCELERATOR (MACA) JTAG/ Nexus DEBUG ARM7 TDMI-S 32-BIT CPU BUS INTERFACE & MEMORY ARBITRATOR ARM INTERRUPT CONTROLLER (AITC) CLOCK & RESET MODULE (CRM) DUAL 12-BIT ADC MODULE TIMER MODULE (TMR) (4 Tmr Blocks) UART MODULE (UART0) ANALOG TRANSMITTER BALUN RF TX/RX SWITCH ANALOG RECEIVER IEEE 802.15.4 TRANSCEIVER ADVANCED SECURITY MODULE (ASM) SYNC SERIAL INTERFACE (SSI/i2S) KEYBOARD INTERFACE (KBI) MC13224V SPI FLASH MODULE (SPIF) ANALOG POWER MANAGEMENT & VOLTAGE REGULATION INTER-IC BUS MODULE (I2C) SERIAL PERIPHERAL INTERFACE (SPI) 96KBYTE SRAM (24K WORDS x 32 BITS) 80KBYTE ROM (20KWORDS x 32 BITS) Buck Regulator 128KBYTE NON-VOLATILE MEMORY (SERIAL FLASH) GPIO and IO CONTROL Figure 2. MC13224V Simplified Block Diagram 2.2 * Features Summary IEEE 802.15.4 standard compliant on-chip transceiver/modem -- 2.4 GHz ISM Band operation -- 16 selectable channels -- Programmable transmitter output power (-30 dBm to +4 dBm typical) -- World-class receiver sensitivity - < -96 dBm typical receiver sensitivity using DCD mode (<1% PER, 20-byte packets) - < -100 dBm typical receiver sensitivity using NCD mode (<1% PER, 20-byte packets) Hardware acceleration for IEEE 802.15.4 applications -- MAC accelerator (sequencer and DMA interface) MC13224V Product Preview, Rev. 1.7 * 4 Freescale Semiconductor UP TO 64 IO PINS UART MODULE (UART1) * * * * * * * -- Advanced encryption/decryption hardware engine (AES 128-bit) Supports standard IEEE 802.15.4 signaling with 250 kbps data rate 32-bit ARM7TDMI-S CPU core with programmable performance up to 26 MHz (24 MHz typical) Extensive on-board memory resources -- 128 Kbyte serial FLASH memory (will be mirrored into RAM) -- 96 Kbyte SRAM -- 80 Kbyte ROM Best-in-class power dissipation -- 21mA typical RX current draw (DCD mode) with radio and MCU active -- 28 mA typical TX current draw with radio and MCU active (coin cell capable) -- 5mA maximum current draw with MCU active (radio off) -- 0.9mA maximum current with MCU idle (radio off) -- 1.1 A maximum Hibernate current (retain 8 Kbyte SRAM contents) -- 0.3A maximum Off current (device in reset) Extensive sleep mode control and variation -- Hibernate and Doze low power modes -- Programmable degree of power down -- Clock management -- Onboard 2kHz oscillator for wake-up timer. -- Optional 32.768 kHz crystal oscillator for accurate real-time sleep mode timing and wake-up with a possible sleep period greater than 36.4 hours -- Wake-up through programmable timer, external real-time interrupts, or ADC timer Extensive MCU peripherals set -- Dedicated 802.15.4 modem/radio interface module (RIF) -- Dedicated NVM SPI interface for managing FLASH memory -- Two dedicated UART modules capable of 2Mbps with CTS/RTS support -- SPI port with programmable master and slave operation -- 8-pin keyboard interface (KBI) supports up to a 4x4 matrix. Also, provides up to 4 asynchronous interrupt inputs for wake-up -- Two 12-bit analog-to-digital converters (ADCs) share 8 input channels -- Four independent 16-bit timers with PWM capability. These can cascade in combinations up to 64-bit operation -- Inter-integrated circuit (I2C) interface -- Synchronous Serial Interface (SSI) with I2S and SPI capability and FIFO data buffering -- Up to 64 programmable I/O shared by peripherals and GPIO Powerful In-circuit debug and FLASH programming available via on-chip debug ports -- JTAG debug port -- Nexus extended feature debug port MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 5 * * * * * * * System protection features -- Low battery detect -- Watchdog timer (COP) -- Sleep mode timer Low external component count -- Only antenna needed for single-ended 50- RF interface (balun in package) -- Only a single crystal is required for the main oscillator; programmable crystal load capacitors are on-chip -- All bypass capacitors in package Supports single crystal reference clock source (typical 24 MHz crystal with 13 - 26 MHz usable) with on-chip programmable crystal load capacitance or external frequency source. Also provides onboard 2kHz oscillator for wake-up timing or an optional 32.768 kHz crystal for accurate low power timing. 2.0V to 3.6V operating voltage with on-chip voltage regulators; down to 1.8V with off-chip regulation Optional buck converter for better battery life. -40C to +105C temperature range RoHS-compliant 9.5mm x 9.5mm x 1.2mm 99-pin LGA package 2.3 High Density, Low Component Count, Integrated IEEE 802.15.4 Solution The MC13224V is more than a high performance, low power platform-in-a-package IEEE 802.15.4 solution. Not only are the transceiver (radio) and MCU on an SoC, the packaged solution contains a 128 Kbyte serial FLASH memory, onboard bypass capacitors for critical nodes, and RF components that present a single-ended 50- interface for an external antenna. The radio is a full differential design with an on-chip transmit/receive (TX/RX) switch, and the PiP also has an onboard balun for differential to singled-ended conversion. On-chip RF matching is also provided to present the proper impedance to the antenna. To further simplify the application, single crystal operation (optimized for 24 MHz) is supported for full radio and MCU operation. If the default 24 MHz crystal is not used, the device supports 13-26 MHz crystals also. The load capacitance to the crystal oscillator is supplied on-chip to eliminate the need for the otherwise required external capacitors. 2.4 Integrated IEEE 802.15.4 Transceiver (Radio and Modem) The MC13224V IEEE 802.15.4 fully-compliant transceiver provides a complete 2.4 GHz radio with 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 5.0 MHz channels and full spread-spectrum encode and decode. The modem supports transmit, receive, clear channel assessment (CCA), Energy Detect (ED), and Link Quality Indication (LQI) as required by the 802.15.4 Standard. MC13224V Product Preview, Rev. 1.7 6 Freescale Semiconductor 2.4.1 RF Interface and Usage The MC13224V RF interface provides for a single-ended, 50- port that connects directly to an antenna. There is an onboard balun that converts the single-ended interface to a full differential, bi-directional, on-chip interface with transmit/receive switch, LNA, and complementary PA outputs. The required port impedance matching is also onboard. This combination allows for a very small footprint and a very low cost RF solution. The receiver demodulator includes a module called the Differential Chip Detector which has two modes of operation: * Non-coherent Detection (NCD) with automatic frequency control (AFC) * Non-coherent Differential Chip Detection (DCD) without AFC IEEE 802.15.4 standard allows a maximum clock drift of 40 ppm (which equals 80 ppm station-to-station). The MC13224V 802.15.4 demodulator includes two different methods of operating in the presence of such large frequency errors, i.e., NCD and DCD. With DCD mode, RX performance loses ~3.5 dB of sensitivity. Alternately, NCD mode provides an increased ~3.5 dB of sensitivity, however, the addition of the AFC increases the demodulator current drain about 3-4 mA. For longer range applications where external amplification may be desired (LNA and/or PA), additional ports are provided for secondary complementary PA outputs. These can be used as a separate PA interface while the single-ended port through the balun is used as an input only. Also, 4 control pins and a regulated 20 mA voltage source are provided to control external components and supply power to the PA outputs. The RF Interface functionality can be summarized as follows: * Programmable output power -- 0 dBm nominal output power, programmable from -30 to +4 dBm * Receive sensitivity (at 1% PER, 20-byte packet) -- < -96 dBm (typical) DCD receive (well above IEEE 802.15.4 specification of -85 dBm) -- < -100 dBm (typical) NCD receive (higher current) * Single-ended 50- antenna port -- Uses integrated transmit/receive (T/R) switch, LNA, and onboard balun. Impedance matching onboard. * Maximum flexibility -- Optionally, single-ended port becomes RF input only and a separate set of full differential PA outputs are provided. Separate input and outputs allow for a variety of RF configurations including external LNA and PA for increased range * Four control signals for external RF components such as a LNA or PA * Regulated voltage source for PA biasing and powering external components 2.4.2 Modem The modem supports the full requirement of the IEEE 802.15.4 Standard to transmit and receive data packets. In additional, the mechanism is present to measure received signal level to provide CCA, ED, and LQI as required by the 802.15.4 Standard. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 7 2.5 * * * * High Performance, Low Power 32-Bit ARM7 Processor The ARM7TDMI-S processor is a member of the 32-bit ARM family of general-purpose 32-bit microprocessors that offers high performance with very low-power consumption A three stage instruction pipeline (fetch, decode, execute) increases the speed of the flow of instructions to the processor Data access can be 8-bit bytes, 16-bit half words, or 32-bit words. Words must be aligned to 4-byte boundaries. Half words must be aligned to 2-byte boundaries The ARM7TDMI-S processor supports two instruction sets, i.e., the 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb mode incorporates 16-bit instructions for higher code density while retaining all the benefits of a 32-bit architecture, i.e., full 32-bit registers, 32-bit operations, and 32-bit memory transfer. The use of the instruction sets can be intermixed for maximizing performance while retaining higher code density ADDR[31:0] Address Incrementer ALU Bus Register Bank 31 x 32-Bit Registers (6 Status Registers) A Bus 32 x 8 Multiplier B Bus Incrementer Bus Address Register PC Bus Barrel Shifter Scan Debug Control 32-Bit Alu Instruction Decoder and Control Logic Write Data Register Instruction Pipeline Read Data Register Thumb Instruction Decoder WDATA[31:0] RDATA[31:0] Figure 3. ARM7TDMI-S 32-Bit CPU Core MC13224V Product Preview, Rev. 1.7 8 Freescale Semiconductor 2.6 Low Power Operation and Power Management The MC13224V is inherently a very low power device, but it also has extensive power management and an onboard buck regulator option to maximize battery life. 2.6.1 Operating Current The MC13224V operating currents are a function of operating mode. There are two basic low power modes of Hibernate and Doze, and both have options of how much RAM contents are retained. The difference between Hibernate and Doze is that Doze mode keeps the primary reference oscillator running. Highest operating current is when the radio is active for transmit or receive. Refer to Section 6.4, "Supply Current Characteristics" for more details and specifications. 2.6.2 Power Management The MC13224V power management is controlled through the Clock and Reset Module (CRM). The CRM is a dedicated module to handle MCU clock, reset, and power management functions which includes control of the power regulators. All these functions have impact on attaining lowest power. 2.6.2.1 CRM Features The CRM features include: * Control of system reset * Control clock gating for power savings * Sleep mode (Hibernate and Doze) management -- Degree of chip power down -- Retention of programmed parameters -- Programmable retention of RAM contents -- Clock management * Wake-up management -- Graceful power-up -- Clock management -- Wake-up via programmable timer or external interrupts. * Wake-up timer -- For Hibernate mode, based on onboard 2 kHz oscillator or optional 32.768 kHz crystal oscillator -- For Doze mode, based on main reference oscillator, typically 24 MHz * Controls reference clocks based on default 24 MHz crystal oscillator or optional 13-26 MHz oscillator with PLL (external filter) for 24 MHz frequency synthesis. * MCU watchdog timer (COP) * Software initiated reset MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 9 * Management control of onboard linear regulators and optional buck regulator 2.6.2.2 CRM Operation The CRM has primary control of the entire system: * Reset and power up -- After release of the hardware RESETB signal, the CRM will perform a power up sequence of the MCU. The linear regulators and clock sources are managed for a graceful start-up of the MCU and its resources. The radio is not powered until needed * Normal operation of MCU -- The clock management of the MCU and its resources are controlled by the CRM. The processor clock is programmable from low frequencies up to the maximum reference frequency (13-26 MHz optional w/24 MHz standard) to allow the application to trade-off processing speed versus power savings * Sleep modes and recovery -- There are two sleep modes of Hibernate and Doze. The primary difference is that Doze mode keeps the reference oscillator running. Both modes can retain critical programmed parameters and have selectable sizes of RAM retention. Hibernate has lowest power, but Doze allows high accuracy sleep timing. The CRM manages the recovery from low power, similar to power-up from reset, providing regulator and clock management. -- Wake-up can be based on external interrupts through 4 KBI inputs -- Wake-up can be from internal interrupts -- Wake-up can be based on an RTI (wake-up) timer. * The RTI timer with 2 possible frequency sources provides a very low power wake-up option from sleep -- One option is an onboard, low accuracy 2 kHz oscillator -- A second option is to add an external 32.768 kHz crystal for the RTI clock source -- A 32-bit timer allows greater than a 36.4 hour wake-up delay with the 32.768 crystal oscillator * Other features of the CRM: -- An optional COP watchdog timer to monitor CPU program activity -- A programmable software reset 2.6.3 Optional Buck Regulator For battery based applications, an optional buck regulator is provided to maximize battery life. Figure 4 shows the configuration of the buck regulator versus the normal connection. An onboard MOSFET is used as a switch with an external 100H inductor and 10F capacitor when the buck regulator is enabled. The buck regulator drops the higher battery voltage to 1.8 - 2.0 Vdc that is applied to the onboard linear regulators. This allows lower net current from the battery to maximize the life of the battery. MC13224V Product Preview, Rev. 1.7 10 Freescale Semiconductor VDD VDD VBATT VBATT L2 COIL_BK NC COIL_BK 100uH LREG_BK_FB LREG_BK_FB MC13224V MC13224V C2 10uF Normal Operation Buck Regulator Figure 4. Optional Buck Regulator 2.6.4 Battery Detect An optional feature of the ADC module is battery voltage detect. Programmable thresholds are provided for an ADC analog sample channel to monitor the battery high voltage and battery low voltage. This feature can be used as a trigger to provide low battery indication, protection for data that may be lost due to end-of-life for the battery, monitoring charging, and controlling buck regulator operation. 2.7 IEEE 802.15.4 Acceleration Hardware The MC13224V provides acceleration hardware for IEEE 802.15.4 applications and this hardware includes 802.15.4 MAC acceleration and AES encryption/decryption. 2.7.1 802.15.4 MAC Accelerator (MACA) Overview The MC13224V contains a hardware block that provides a low-level MAC and PHY link controller, which together with software running on the ARM core, implements the baseband protocols and other low-level link routine control and link control. Components of the MACA include a sequencer/controller (with timers), TX and RX packet buffers, DMA block, frame check sequence (FCS) generator/checker, and control registers. Figure 5 shows a MACA simplified block diagram. As part of the 802.15.4 protocol, packets are generated and transmitted, packets are received and verified, and channel energy is measured via a clear channel assessment (CCA). Also, combinations or sequences of events are required as part of the protocol such as an ACK response following a received packet. The MACA facilitates these activities via control of the transceiver and off loads the functions from the CPU. A dedicated DMA function moves data between the MACA buffers and RAM on a cycle steal basis and does not require intervention from the CPU. The MACA is responsible for construction of packets for TX including FCS, and for parsing the received packets. The MACA will also handle ACKs and TxPoll sequences independent of the ARM processor. During TX the MACA will construct the entire packet. This includes preamble and SFD (start of frame MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 11 delimiter). During receive, the modem will recognize preamble and SFD, then the MACA will begin receiving the packet with the first bit of frame length, and finally, will check the FCS. Sequencer Timers Control Registers To Transceiver Modem TX Packet Buffer RX Packet Buffer DMA To MCU Bus MACA FCS Generator/ Checker Figure 5. MAC Accelerator Simplified Block Diagram NOTE The radio can receive packets of either mode without prior indication of the incoming packet mode. 2.7.1.1 MACA Features In order to reduce CPU load, the MACA module has embedded features for controlling parts of the IEEE 802.15.4 PHY and MAC layer requirements. The MACA core features include: * Sequence Manager sequences / auto sequences -- RX only -- TX only -- Automatic acknowledgment frame reception on transmitted packets -- Automatic acknowledgment frame transmission on received packets -- Auto-RX for continuous reception as coordinator -- Auto sequence for transmitted MAC data.request -- Assist for efficient response to MAC data.request -- Embedded channel assessment in sequence -- Support for sequences with slotted mode access -- Timer triggered and immediately executed actions -- Support for extended RX for reception in random backoff and battery life extension -- Support for promiscuous mode * Programmable auto sequence timing - Each CCA, RX, or TX event is an independent operation. The radio gets through a power-up or "warm-up" sequence for each operation (including VCO), MC13224V Product Preview, Rev. 1.7 12 Freescale Semiconductor * * * * * * * and there is also a power-down or "warm-down" time. Sequences are combinations of radio operations and are highly configurable. -- RX warm-up is 72 s -- TX warm-up is 92 s -- Turnaround times - The IEEE 802.15.4 Standard requires a TX-to-RX or a RX-to-TX turnaround time to be less than or equal to 12 symbols times (192 s). - Best practice for maximum station-to-station performance is to minimize TX-to-RX turnaround time and to maximize (within spec) RX-to-TX turnaround time. - Auto sequences should use recommended turnaround times of: a) 11 symbols times (176 s) RX-to-TX b) 96 s TX-to-RX. Dedicated DMA for transfer of TX/RX data from/to RAM (minimum bus clock of 2 MHz for 802.15.4 modem operation) Maskable, event-driven interrupt generation Address header filtering for received packets. A promiscuous mode allows bypass of the filtering for monitoring network traffic Packet manager -- Handles preamble data -- Handles frame check sequence (FCS) a.k.a CRC -- Embedded header filter for received packets Beacon Support Mode Control/status registers mapped into CPU memory map 32-Bit random number generator -- Runs at the bus clock rate, a 32-bit Linear Feedback Shift Register (LFSR) can be set with a seed value and uses a 32-bit primitive polynomial. A 32-bit random number is fetched with every read of the proper control register 2.7.2 Advanced Security Module (ASM) The IEEE 802.15.4 Standard and the ZigBee Standard both provide for optional use of data encryption.The ASM engine is a hardware block that accelerates encryption/decryption using the Advanced Encryption Standard (AES). The engine can perform "Counter" (CTR) and Cipher Block Chaining (CBC) encryption. The combination of these two modes of encryption are known as CCM mode encryption. CCM is short for Counter with CBC-MAC. CCM is a generic authenticate and encrypt block cipher mode. CCM is only defined for use with 128 bit block ciphers, such as AES. The definition of CCM mode encryption is documented in the NIST publication SP800-38C. The ASM has the following features: * * * 32-Bit wide bus interface CTR encryption in 13 clock cycles CBC encryption in 13 clock cycles MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 13 * * * * Encrypts 128 bits as a unit The 128-bit registers are aligned on quad word boundaries (16 byte) Self-test mode Maskable "action complete" interrupt 3 3.1 Memory RAM and ROM The MC13224V memory resources consist of RAM, ROM, and serial FLASH. The RAM and ROM features include: * 96 Kbytes RAM. -- RAM0: 8 Kbytes, 2 Kwords (2048 x 32 bits) -- RAM1: 24 Kbytes, 6 Kwords (6144 x 32 bits) -- RAM2: 32 Kbytes, 8 Kwords (8192 x 32 bits) -- RAM3: 32 Kbytes, 8 Kwords (8192 x 32 bits) * All read or write accesses require a minimum of two system clock cycles * Stall signal generated for read after write cycles * Clock is enabled only on the accessed memory device for low power consumption * RAMs have been divided to allow for power savings. While sleeping, the above RAM blocks can be turned off (combinations include 8, 32, 64, and 96 Kbytes active) and the RAM remainder can be placed in a low voltage mode for data retention. If more RAMs are turned on, then less battery life will be achieved. Depending on the amount of RAM powered during sleep, the boot time may be longer with less RAM as the non-powered RAM must be reloaded from FLASH. * 80 Kbytes ROM -- 20 Kwords (20480 x 32 bits) -- Initially contains bootstrap code, 802.15.4 MAC (no security), UART driver, and SPI driver. The MAC software builds on the lower level hardware capability of the transceiver and MACA. All code except the bootstrap is "patchable". -- Can be extended later to communications stack software and NVM services (erase, program, and read routines) 3.2 Serial FLASH (NVM) The MC13224V also contains a 128 Kbyte serial FLASH memory that can be mirrored into the 96 Kbyte RAM. The serial FLASH is accessed via an internal dedicated SPI module (SPIF). The FLASH erase, program, and read capability are programmed through the SPIF port. The FLASH is accessed at boot time to load/initialize RAM. All actual CPU program and data access is from RAM or ROM. MC13224V Product Preview, Rev. 1.7 14 Freescale Semiconductor 4 MCU Peripherals BATTERY DETECT DUAL 1 2 -B IT ADC M O DULE The MC13224V has a rich set of MCU peripherals. Figure 6 shows the peripheral modules. F ro m CRM T IM E R M O DULE (T M R ) (4 T m r B lo c k s ) UART M O DULE (U A R T 0 ) JTAG / N e xu s DEBUG ARM7 T D M I-S 3 2 -B IT CPU BUS IN T E R F A C E & MEMORY A R B IT R A T O R ARM IN T E R R U P T CO NTRO LLER (A IT C ) S Y N C S E R IA L IN T E R F A C E (S S I/i2 S ) KEYBOARD IN T E R F A C E (K B I) IN T E R -IC B U S M O DULE (I2 C ) S E R IA L P E R IP H E R A L IN T E R F A C E (S P I) G P IO a n d IO CO NTRO L SPI FLASH M O DULE (S P IF ) Figure 6. MCU Peripherals MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 15 UP TO 64 IO PINS UART M O DULE (U A R T 1 ) 4.1 Parallel IO (GPIO) The parallel I/O features include: * A total of 64 general-purpose I/O pins * Individual control (direction and output state) for each pin when in GPIO mode * Pad hysteresis enables * Software-controlled pull-ups/pull-downs on each input pin * When not used as GPIO, the IO provide alternative functions -- Debug ports for JTAG (four signals) and Nexus (fourteen signals) modules -- Four control signals for external RF components such as an LNA, PA, and antenna switch -- Eight analog inputs for ADC input channels -- Four signals for ADC reference voltages -- Eight signals for UART1 and UART2 -- Two I2C signals -- Four timer block signals -- Four SPI block signals -- Four SSI block signals -- Eight KBI signals * Eight KBI pins are kept alive during Hibernate or Doze. Four KBI are output and four are inputs. The input can be used as wake-up interrupts 4.2 Keyboard Interface (KBI) The MC13224V designates 8 pins (KBI_0 to KBI_7) as a keyboard interface, where four of these signals typically are outputs and four are inputs (KBI_4 to KBI_7) that support interrupts. These 8 pins could typically be used as a matrix interface to support up to 16 switches or buttons, such as a keypad. These signals can also be used as general purpose IO if a keyboard is not present. During Hibernate or Doze, the KBI are unique in that they are kept alive. Four KBI are outputs and four KBI are inputs. The inputs can be enabled as asynchronous interrupts to wake-up the MC13224V from the sleep mode. MC13224V Product Preview, Rev. 1.7 16 Freescale Semiconductor 4.3 Timer (TMR) Module The MC13224V provides a timer module (TMR) that contains four identical counter/timer groups. Each group is capable of many variants of input capture, output compare and pulse-width modulation. The wide range of operational modes is useful for many control and sensor applications. Figure 7 shows a block diagram of an individual timer group. CMPLD1 COMP1 Comparator CMPLD2 M U X OFLAG Output COMP2 Comparator MCU DATA BUS LOAD COUNTER HOLD CAPTURE Other Counter Reference Peripheral Reference Clock M U X External Prescaler STATUS AND CONTROL Figure 7. Timer Group Block Diagram Each 16-bit counter/timer group contains a prescaler, a counter, a load register, a hold register, a capture register, two compare registers, and status and control registers. * Load Register -- Provides the initialization value to the counter when the counter's terminal value has been reached * Hold Register -- Captures the counter's value when other counters are being read. This feature supports the reading of cascaded counters * Capture Register -- Enables an external signal to take a snap shot of the counter's current value * COMP1 and COMP2 Registers -- Provides the values to which the counter is compared. If a match occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated (if enabled), and the new compare value is loaded into the COMP1 or COMP2 registers from CMPLD1 and CMPLD2 if enabled MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 17 * * * The Prescaler provides different time bases useful for clocking the counter/timer The Counter provides the ability to count internal or external events Control and Status Registers -- Provides operational mode control of the counter, status, clock source control, interrupt control, and external interface control Four GPIO pins (TMR0 -TMR3) are programmable and can be used with any counter/timer group. The TMR module feature include: * Four 16-bit counters/timers groups * Up/down count * Counters are cascadable for up to 64 bit delay counter * Programmable count modulo. * Peripheral reference clock equates to reference oscillator frequency * External clock max count rate equals peripheral clock divided by 2 * Internal clock max count rate equals peripheral clock. * Count once or repeatedly * Counters are preloadable * Compare registers are preloadable * Counters share available 4 GPIO pins (programmable as inputs or outputs and programmable for falling or rising edge) * Separate prescaler for each counter * Each counter has capture and compare capability * Optional input glitch filter * Functional modes include stop, count, edge-count, gated-count, quadrature-count, signed-count, triggered-count, one-shot, cascade-count, pulse-output, fixed frequency PWM, and variable-frequency PWM 4.4 UART Modules The MC13224V has two universal asynchronous receiver/transmitter (UART) modules. Each UART has an independent fractional divider, baud rate generator that is clocked by the peripheral bus clock (typically 24 MHz) which enables a broad range of baud rates up to 1,843.2 kbaud. Transmit and receive use a common baud rate for each module. Each UART provides the following features: * 8-bit only data * One or two stop bits * Programmable parity (even, odd, and none) * Four-wire serial interface (RXD, TXD, RTS, and CTS) * Hardware flow control support for RTS and CTS signals * 32-byte receive FIFO and 32-byte transmit FIFO MC13224V Product Preview, Rev. 1.7 18 Freescale Semiconductor * * * * * * * * * Programmable sense for RTS/CTS pins (high true/low true) Status flags for various flow control and FIFO states Receiver detects framing errors, start bit error, break characters, parity errors, and overrun errors. Voting logic for improved noise immunity (16X/8X oversampling) Maskable interrupt request Time-out counter, which times out after eight non-present characters Receiver and transmitter enable/disable Low-power modes Baud rate generator to provide any multiple-of-2 baud rate between 1.2 kbaud and 1,843.2 kbaud 4.5 Inter-Integrated Circuit (I2C) Module The MC13224V provides an Inter-Integrated Circuit (I2C) module for the I2C which is a two-wire, serial data (SDA) and serial clock (SCL), bidirectional serial bus. The I2C allows for data exchange between the MC13224V and other devices such as MCUs, serial EEPROM, serial ADC and DAC devices, and LCDs. The I2C minimizes interconnections between devices and is a synchronous, multi-master bus that allows additional devices to be connected and still handle system expansion and development. The bus includes collision detection and arbitration to prevent data corruption if two or more masters attempt to simultaneously control the I2C. The I2C module is driven by the peripheral bus clock (typically 24 MHz) and the SCL bit clock is generated from a prescaler. The prescaler divide ratio can be programmed from 61,440 to 160 (decimal) which gives a maximum bit clock of 150 kbps. The I2C module supports the following features: * Two-wire (SDA and SCL) interface * Multi-master operation * Master or slave mode * Arbitration lost interrupt with automatic mode switching from master to slave * Calling address identification interrupt * START and STOP signal generation/detection * Acknowledge bit generation/detection * Bus busy detection * Software-programmable bit clock frequency up to 150 kbps * Software-selectable acknowledge bit * On-chip filtering for spikes on the bus MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 19 4.6 Serial Peripheral Interface (SPI) Modules The MC13224V has two SPI modules that use a common architecture 4.6.1 External SPI Module The MC13224V offers a dedicated Serial Peripheral Interface (SPI) module for external use. The SPI is a high-speed synchronous serial data input/output port used for interfacing with serial memories, peripheral devices, or other processors. The SPI allows a serial bit stream of a programmed length (1 to 32 bits) to be shifted simultaneously into and out of the device at a programmed bit-transfer rate (called 4-wire mode). There are four pins associated with the SPI port (SPI_SCK, SPI_MOSI, SPI_MISO, and SPI_SS). The SPI module can be programmed for master or slave operation. It also supports a 3-wire mode where for master mode the MOSI becomes MOMI, a bidirectional data pin, and for slave mode the MISO becomes SISO, a bidirectional data pin. In 3-wire mode, data is only transferred in one direction at a time. The SPI bit clock is derived from the peripheral reference clock (typically 24 MHz with a maximum of 26 MHz). A prescaler divides the peripheral reference clock with a programmed divide ratio from 2 to 256. Typical bit clock range will be from 12 MHz to 93.75 kHz. The SPI has the following features: * Master or slave mode operation * Data buffer is 4 bytes (32 bits) in length * SPI transfer length programmable from 1 to 32 bits * MSB-first shifting * Programmable transmit bit rate (typically 12 MHz max) * Serial clock phase and polarity options * Full-duplex (4-wire) or bidirectional data (3-wire) operation * SPI transaction can be polled or interrupt driven * Slave select signal * Low Power (SPI Master uses gated clocks. SPI Slave clock derived completely from SPI_SCK.) 4.6.2 SPI FLASH Module (SPIF) The SPIF is an internal SPI block dedicated to control, reading, and writing of the serial FLASH memory (NVM). It uses the same architecture as the general SPI block, but will be limited by the characteristics of the FLASH SPI interface. MC13224V Product Preview, Rev. 1.7 20 Freescale Semiconductor 4.7 Synchronous Serial Interface (SSI) Module The MC13224V provides a versatile Synchronous Serial Interface (SSI) which is a full-duplex, serial port that allows communication with a variety of serial devices. These serial devices can be digital signal processors (DSPs), MCUs, peripherals, popular industry audio CODECs, and devices that implement the Inter-Integrated Circuit sound bus standard (I2S). The SSI typically transfers samples in a periodic manner and it consists of independent transmitter and receiver sections with common clock generation and frame synchronization. The external signals include the bit clock (SSI_BITCK), frame sync (SSI_FSYN), RX data (SSI_RX), and TX data (SSI_TX). The SSI has the following basic operating modes all with synchronous protocol: * Normal mode -- The simplest SSI mode transfers data in one time slot per frame * Network mode -- Creates a Time Division Multiplexed (TDM) network, such as a TDM CODEC network or a network of DSPs * Gated Clock mode -- Connects to SPI-type interfaces on MCUs or external peripheral chips With its multi-modes, the SSI can be programmed for two very useful functions: * A second SPI port augmenting the MC13224V SPI module * I2S interface - the SSI is capable of generating the required clock frequencies and data format to drive a serial stereo audio DAC The SSI includes the following features: * Synchronous transmit and receive sections with shared internal/external clocks and frame syncs operating in Master or Slave mode * Normal mode operation using frame sync * Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots * Gated Clock mode operation requiring no frame sync * Transmit and Receive FIFOs. Each of the FIFOs is 8x24 bits. The TX/RX FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception * Programmable data interface modes such as I2S, LSB, MSB aligned * Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits) * Program options for frame sync and clock generation * Programmable I2S modes (Master, Slave or Normal). Oversampling clock available as output in I2S Master mode * External SSI_BITCLK input for use in I2S Master mode. Programmable oversampling clock of the sampling frequency available as output in master mode, when operated in sync mode * Programmable internal clock divider * Time Slot Mask Registers for reduced CPU overhead (for both TX and RX) * SSI power-down feature MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 21 4.8 Analog-to-Digital Converter (ADC) Module The MC13224V ADC module provides two 12-bit analog-to-digital converters (ADC1 and ADC2) with 8 external channels (ADC7 - ADC0) that can be multiplexed to either ADC. ADC1 can also sample the battery voltage for monitoring purposes. External pins (ADC2_VREFH, ADC2_VREFL, ADC1_VREFH, and ADC1_VREFL) are provided for independent ADC reference voltages. The minimum sample time is 20 us. Figure 8 shows a block diagram of the ADC module. Each ADC can be programmed to scan multiple selected channels on a timed basis. The primary clock to the ADC module is the peripheral reference clock (typically 24 MHz). For the time period between scan sequences, the primary clock is first divided by an 8-bit prescale (1-255), and the derived clock drives both the 32-bit delay timer and the ADC sequencer. Each ADC has its own delay timer and sequencer. Once a scan sequence has been initiated, all selected channels can be sampled. Registers are provided to define thresholds that can be enabled for the sampled channels. A threshold can be assigned to a specific channel and can be programmed to be a less-than or greater-than threshold. Multiple thresholds can be assigned to a single channel. Warm-up of the analog portion of the ADC circuitry is provided for power management, and a separate 300 kHz ADC clock must be programmed via its own divider. The battery monitor has two (2) dedicated threshold registers to set the high and low limits of the battery sample channel. Sample values are stored in a 8x16-bit FIFO. The FIFO accumulates samples from both ADCs, and the 12-bit sample value and a 4-bit channel tag are saved for each sample. The FIFO is read by the CPU from a register address. The module can be programmed to interrupt the processor based on the timed sample activity. Sample activity, sequencer activity, or FIFO "fullness" can all be enabled to generate an interrupt. The ADCs can also be overridden to sample on command as opposed to sequencer, time-based activity. MC13224V Product Preview, Rev. 1.7 22 Freescale Semiconductor Control Override Mode Sequencer 1 M U X ADC1 Enable ADC1 Mux Sel 32-Bit Timer ADC1 Control Registers MCU DATA BUS FIFO (8 x 16-Bit, 12-bit value + 4bit channel Tag) M U X ADC Clock Compare Battery Analog Channels ADC0 - ADC7 ADC2 Control Override Mode Sequencer 2 M U X M U X ADC2 Enable ADC2 Mux Sel ADC Clock Prescaler 32-Bit Timer Divider Analog Peripheral Reference Clock 300 kHz Figure 8. ADC Module Block Diagram The ADC has the following features: * 12 bit resolution * Separate input voltage ranges: VREFH to VREFL. Max input of 3.6 Vdc. Min input of 0.0 Vdc * Typical resolution of 10.5 bits * Conversion rate has a minimum sample time of 20us. Effective number of bits varies with sample rate. * 8-bit prescaler to provide the time base for the 32-bit timers * Two independent channels, each with a 32-bit timer * Simultaneous channel sampling or sequential channel sampling with dual ADCs * On-board battery detect sample channel * Primary ADC has 9 channels. 8 external channels plus battery detect * Secondary ADC has 8 external channels * Active channels for each ADC are programmable * A maximum of 8 active monitors can generate a interrupt request * A 8-deep FIFO for recording data (12-bit sample plus 4-bit channel tag) * Interrupt requests can be generated by the channel compare values, end-of-scan sequence, out-of-range, FIFO status, and 32-bit timers * Independent soft reset MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 23 5 Pin Assignments and Connections ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7_RTCK TDO TDI TCK TMS UART2_RTS UART2_CTS UART2_RX UART2_TX ADC2_VREFH ADC1_VREFH ADC1_VREFL ADC2_VERFL RF_RX_TX RX_ON RF_GND ANT_2 ANT_1 RF_BIAS PA_POS PA_NEG TX_ON RESETB XTAL_24_IN XTAL_24_OUT 64 63 1 2 3 4 5 6 7 8 9 10 120 11 12 13 14 15 16 17 129 121 122 123 124 102 103 104 105 106 84 85 86 87 88 75 76 77 78 79 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 Substrate GND Pads 46 45 44 43 42 41 40 39 38 37 36 93 94 95 96 97 111 112 113 114 115 130 131 132 133 MC13224V 18 19 20 21 22 23 24 25 26 27 28 29 30 31 35 34 33 32 XTAL_32_OUT XTAL_32_IN RF_PLL_FLT VBATT LREG_BK_FB COIL_BK KBI_0_HST_WK KBI_1 KBI_2 KBI_3 KBI_4 KBI_5 KBI_6 KBI_7 SSI_TX SSI_RX Figure 9. MC13224V Pinout (Top View; active bottom pads shown) 24 UART1_RTS UART1_CTS UART1_RX UART1_TX I2C_SDA I2C_SCL TMR3 TMR2 TMR1 TMR0 SPI_SCK SPI_MOSI SPI_MISO SPI_SS SSI_BITCK SSI_FSYN Notes: 1. Only active substrate bottom pads are shown. 2. Additional substrate pads (see mechanical drawings) no connect and are for mechanical attach only. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 5.1 Pin Definitions Table 2. Pin Function Description Table 2 details the MC13224V pinout and functionality. Description1 ADC analog input Channel 0 / GPIO30 ADC analog input Channel 1/ GPIO31 ADC analog input Channel 2/ GPIO32 ADC analog input Channel 3/ GPIO33 ADC analog input Channel 4/ GPIO34 ADC analog input Channel 5/ GPIO35 ADC analog input Channel 6/ GPIO36 ADC analog input Channel 7 / ReTurn ClocK / GPIO37 JTAG Test Data Output / GPIO49 Pin # 1 Pin Name ADC0 Type Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Analog Input or Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Functionality ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. ADC sample channel can be used by either ADC1 or ADC2. Alternately, the signal returns TCK for JTAG to support adaptive clocking. JTAG debug port serial data output. 2 ADC1 3 ADC2 4 ADC3 5 ADC4 6 ADC5 7 ADC6 8 ADC7_RTCK 9 10 11 12 13 14 15 16 TDO TDI TCK TMS UART2_RTS UART2_CTS UART2_RX UART2_TX JTAG Test Data Input / GPIO48 JTAG debug port serial data input. JTAG Test Clock Input / GPIO47 JTAG debug port clock input. JTAG Test Mode Select Input / GPIO46 JTAG debug port test mode select input. UART2 Request to Send input / UART2 RTS control input. GPIO21 UART2 Clear to Send output / GPIO20 UART2 CTS control output. UART2 RX data input / GPIO19 UART2 receive data input. UART2 TX data output / GPIO18 UART2 transmit data output. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 25 Table 2. Pin Function Description (continued) Pin # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name UART1_RTS UART1_CTS UART1_RX UART1_TX I2C_SDA I2C_SCL TMR3 TMR2 TMR1 TMR0 SPI_SCK SPI_MOSI SPI_MISO SPI_SS SSI_BITCK SSI_FSYN SSI_RX SSI_TX KBI_7 KBI_6 Type Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Description1 Functionality UART1 Request to Send input / UART1 RTS control input. GPIO17 UART1 Clear to Send output / GPIO16 UART1 CTS control output. UART1 RX data input / GPIO15 UART1 receive data input. UART1 TX data output / GPIO14 I2C Bus data / GPIO13 I2C Bus clock / GPIO12 Timer 3 IO signal / GPIO11 Timer 2 IO signal / GPIO10 Timer 1 IO signal / GPIO9 Timer 0 IO signal / GPIO8 SPI Port clock / GPIO7 SPI Port MOSI/ GPIO6 SPI Port MISO / GPIO5 SPI Port SS / GPIO4 SSI Bit Clock / GPIO3 SSI Frame Sync / GPIO2 SSI RX data input / GPIO1 SSI TX data output / GPIO0 Keyboard Interface Bit 7 / GPIO29 Keyboard Interface Bit 6 / GPIO28 UART1 transmit data output. I2C bus signal SDA I2C bus signal SCL Pin is used as counter output or counter input clock. Pin is used as counter output or counter input clock. Pin is used as counter output or counter input clock. Pin is used as counter output or counter input clock. SPI port clock. SPI Port Master Out Slave In (MOSI) data signal. SPI Port Master In Slave Out (MISO) data signal. SPI Port Slave Select (SS) signal. SSI serial TX/RX clock and is bi-directional. SSI frame sync for data (RX or TX) and is bi-directional. SSI serial RX data input. SSI serial TX data output. Asynchronous interrupt input. Asynchronous interrupt input. MC13224V Product Preview, Rev. 1.7 26 Freescale Semiconductor Table 2. Pin Function Description (continued) Pin # 37 38 39 40 41 42 Pin Name KBI_5 KBI_4 KBI_3 KBI_2 KBI_1 KBI_0_HST _WK COIL_BK LREG_BK_FB Type Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Power Switch Output Power Input Description1 Keyboard Interface Bit 5 / GPIO27 Keyboard Interface Bit 4 / GPIO26 Keyboard Interface Bit 3 / GPIO25 Keyboard Interface Bit 2 / GPIO24 Keyboard Interface Bit 1 / GPIO23 Functionality Asynchronous interrupt input. Asynchronous interrupt input. Used as output for keyboard interface. Used as output for keyboard interface. Used as output for keyboard interface. Keyboard Interface Bit 0 / HoST Used as output for keyboard interface / Walk-up output / GPIO22 Alternative function as a wake-up output (based on a timer) to external device. Buck converter coil drive output Onboard buck converter connection to external coil, driven by onboard MOSFET. Voltage input to onboard regulators, buck regulator feedback voltage * When using onboard buck converter, connect to load side of coil. * When not using buck converter, connect to VBATT. 43 44 45 VBATT Power Input High side supply voltage to buck Connect to battery. regulator switching MOSFET and IO buffers PLL filter connection * Connection for PLL filter (Type 2, 2nd Order) when using primary crystal with frequency other than 24 MHz (13-26 MHz). * No Connect for 24 MHz crystal. Connect to 32.768 kHz crystal Connect to 32.768 kHz crystal * Connect to 13-26 MHz crystal (24 MHz default). * No load capacitor required * Do not load with any capacitance. * Connect to 13-26 MHz crystal (24 MHz default). * No load capacitor required * Do not load with any capacitance. Active low, asynchronous reset Programmable control pin 46 RF_PLL_FLT Analog Voltage 47 48 49 XTAL_32_IN XTAL_32_OUT XTAL_24_OUT Analog Input Optional 32.768 kHz crystal oscillator input Analog Output Optional 32.768 kHz crystal oscillator output Analog Output Primary 24 MHz crystal oscillator output 50 XTAL_24_IN Analog Input Primary 24 MHz crystal oscillator input 51 52 RESETB TX_ON Digital Input Digital Input/Output System reset input Control output for external RF component / GPIO44 MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 27 Table 2. Pin Function Description (continued) Pin # 53 Pin Name PA_NEG Type RF Output Description1 RF power amplifier (PA) ouput negative Functionality * Open drain. Must be connected to RF_BIAS through a bias network. * Only used for external dual port operation. * Do not use for single port operation. No Connect. * Open drain. Must be connected to RF_BIAS through a bias network. * Only used for external dual port operation. * Do not use for single port operation. No Connect. When using dual port operation, tie to PA_POS and PA_NEG through bias networks. Programmable control pin. Programmable control pin. Connect to ground VSS. Programmable control pin. * Interfaces to onboard balun. 50 impedance * Full bidirectional port with onboard T/R switch. * Used as single-ended RF input port for dual port operation with PA_NEG and PA_POS PA outputs. 54 PA_POS RF Output RF power amplifier (PA) ouput positive 55 56 57 58 59 60 RF_BIAS ANT_1 ANT_2 RF_GND RX_ON RF_RX_TX Analog Power Analog VDD regulator output Output Digital input / Output Digital input / Output Power Input Digital input / Output RF Input/Output Control output for external RF component / GPIO42 Control output for external RF component / GPIO43 RF ground. Control output for external RF component / GPIO45 RF single-ended, single port input and ouput 61 ADC2_VREFL Analog Input Low reference voltage for ADC2 VREFL for ADC2. or Digital Input / GPIO39 / Output Analog Input Low reference voltage for ADC1 VREFL for ADC1. or Digital Input / GPIO41 / Output Analog Input High reference voltage for or Digital Input ADC1 / GPIO40 / Output VREFH for ADC1. 62 ADC1_VREFL 63 ADC1_VREFH 64 ADC2_VREFH Analog Input Low reference voltage for ADC2 VREFH for ADC2. or Digital Input / GPIO38 / Output Power input Power input Power input External package GND pads. Common VSS. External package GND pads. Common VSS. External package GND pads. Common VSS. Connect to ground. Connect to ground. Connect to ground. 75-79 84-88 93-97 VSS VSS VSS MC13224V Product Preview, Rev. 1.7 28 Freescale Semiconductor Table 2. Pin Function Description (continued) Pin # 102 103 104106 111 112 113 114 115 120 121 122 123 124 129 130 131 132 Pin Name MDO01 MDO00 VSS MDO03 MDO02 MSEO1_B MSEO0_B VSS MDO05 MDO04 RDY_B EVTO_B DIG_REG MDO07 MDO06 MCKO EVTI_B Type Digital Input/Output Digital Input/Output Power input Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Power input Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Power Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Description1 Functionality Message Data Out Bit 1 output / Nexus debug port message data output Bit 1. GPIO52 Message Data Out Bit 0 output / Nexus debug port message data output Bit 0. GPIO51 External package GND pads. Common VSS. Connect to ground. Message Data Out Bit 3 output / Nexus debug port message data output Bit 3. GPIO54 Message Data Out Bit 2 output / Nexus debug port message data output Bit 2. GPIO53 Message Start / End Out Bit 1 output / GPIO60 Message Start / End Out Bit 0 output / GPIO59 External package GND pads. Common VSS. Nexus debug port message start / end output Bit 1. Signal is active low. Nexus debug port message start / end output Bit 0. Signal is active low. Connect to ground. Message Data Out Bit 5 output / Nexus debug port message data output Bit 5. GPIO56 Message Data Out Bit 4 output / Nexus debug port message data output Bit 4. GPIO55 Ready output / GPIO61 Event Out output / GPIO62 Digital core logic VDD supply. Nexus debug port ready output. Signal is active low. Nexus debug port event out output. Signal is active low. 1.2 Vdc internally regulated VDD supply to digital logic core. No Connect,. For test only Message Data Out Bit 7 output / Nexus debug port message data output Bit 7. GPIO58 Message Data Out Bit 6 output / Nexus debug port message data output Bit 6. GPIO57 Message Clock Out output / GPIO50 Event In input / GPIO63 Nexus debug port message clock output. Nexus debug port event in input. Signal is active low. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 29 Table 2. Pin Function Description (continued) Pin # 133 Pin Name NVM_REG Type NVM Power Output Description1 FLASH (NVM) VDD supply. Functionality VDD supply to FLASH. Typically No Connect. Can be connected to VDD when regulated 1.8Vdc mode is used. These pads are provided for extra mechanical attach strength to meet demanding requirements of drop tests. 65-74, NC 80-83, 89-92, 98-101, 107-110, 116-119, 125-128, 134-145 1 No Connect Pins described as GPIO have an alternative general purpose I/O function. 5.2 Hardware Development Interface Interconnects The MC13224V supports two development hardware interfaces. 5.2.1 ARM JTAG Interface Connector The MC13224V supports connection to a subset of the defined ARM JTAG connector. The JTAG hardware interface uses a 20-pin header with a standard 0.1 inch spacing. Table 3 shows how the MC13224V pins are connected to the associated JTAG header pinouts if the JTAG connector is provided on the application. Table 3. ARM JTAG 20-Pin Connector Assignments Name1 VBATT NC2 TDI TMS TCK RTCK TDO RESET3 NC NC 1 2 Pin # 1 3 5 7 9 11 13 15 17 19 Pin # 2 4 6 8 10 12 14 16 18 20 Name VBATT GND GND GND GND GND GND GND GND GND NC = No Connect. MC13224V does not support separate JTAG reset TRST. 3 VBATT through a 100k- pullup. MC13224V Product Preview, Rev. 1.7 30 Freescale Semiconductor 5.2.2 Nexus Mictor Interface Connector The MC13224V also supports connection to a subset of the defined Nexus Mictor connector. The hardware interface is a 38-pin Mictor target connector. Table 4 shows the device pins that are connected to the associated Mictor pin outs if the Mictor connector is used. Table 4. Nexus 38-Pin Mictor Connector Assignments Name1 NC NC NC NC VBATT(pullup)2 TDO NC TCK TMS TDI RESET4 NC NC NC NC NC NC NC NC 1 2 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Name NC NC RTCK NC EVTI_B VBATT3 RDY_B MDO07 MDO06 MDO05 MDO04 MDO03 MDO02 MDO01 MDO00 EVTO_B MCKO MSEO1_B MSEO0_B NC means No Connect. VBATT through a 100k- pullup. 3 VBATT isolated by a 1k- resistor. 4 VBATT through a 100k- pullup. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 31 6 System Electrical Specification This section details maximum ratings for the 99-pin LGA package and recommended operating conditions, DC characteristics, and AC characteristics. 6.1 LGA Package Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maximum rating is not guaranteed. Stress beyond the limits specified in Table 5 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VBATT) or the programmable pull-up resistor associated with the pin is enabled. Table 5 shows the maximum ratings for the 99-Pin LGA package. Table 5. LGA Package Maximum Ratings Rating Maximum Junction Temperature Storage Temperature Range Moisture Sensitivity Level Reflow Soldering Temperature (for reflow soldering profile and other LGA module reference information, see Freescale application note, AN3311) Power Supply Voltage Digital Input Voltage RF Input Power Instantaneous Maximum Current (Single Pin Limit) VBATT, VDDINT Vin Pmax ID Symbol TJ Tstg Value 125 -55 to 125 MSL3-260 250 Unit C C C -0.3 to 3.7 -0.3 to (VDDINT + 0.2) 10 TBD Vdc Vdc dBm mA Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection. MC13224V Product Preview, Rev. 1.7 32 Freescale Semiconductor 6.2 Recommended Operating Conditions Table 6. Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Power Supply Voltage Single un-regulated source (VBATT and LREG_BK_FB tied common to VDD) Single regulated source (VBATT, LREG_BK_FB, and NVM_REG tied common to VDD) Onboard buck with un-regulated source (VBATT tied to VDD) Input Frequency Operating Temperature Range Logic Input Voltage Low Logic Input Voltage High RF Input Power Crystal Reference Oscillator Frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) fin TA VIL VIH Pmax fref VDD 2.0 3.6 Vdc 1.7 1.8 1.9 Vdc 2.1 2.405 -40 0 70% VBATT 13 25 24 3.6 2.480 +105 30% VBATT VBATT 10 26 Vdc GHz C V V dBm MHz 6.3 DC Electrical Characteristics Table 7. DC Electrical Characteristics (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, unless otherwise noted) Characteristic Power Supply Voltage1 (voltage applied to power input pins) VBATT (pin 45) LREG_BK_FB (pin 44) NVM_REG (pin 133) High impedance (off-state) leakage current (per pin) (VIn = VDD or VSS, all input/outputs, device must not be in low power mode) Input Current (VIN = 0 V or VDDINT) (VIn = VDD or VSS, all input/outputs, device must not be in low power mode) Input Low Voltage (All digital inputs) Symbol Min Typ Max Unit VDD 1.7 1.7 1.7 - 2.7 2.7 1.8 - 3.6 3.6 1.9 1.0 Vdc Vdc Vdc A |IOZ| IIN VIL 0 - 1.0 30% VBATT VBATT -- A V Input High Voltage (all digital inputs) Input hysteresis (all digital inputs) VIH Vhys 70% VBATT 0.06 x VDD - V V MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 33 Table 7. DC Electrical Characteristics (continued) (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, unless otherwise noted) Characteristic Internal pullup and pulldown resistors2 (all port pins and IRQ) Maximum total IOH for all port pins Output High Voltage (IOH = -5 mA) (All digital outputs) Output Low Voltage (IOL = 5 mA) (All digital outputs) Maximum current in/out per IO pin Maximum total IOL for all IO pins Input capacitance (all non-supply pins) 1 Symbol RPU |IOHT| VOH VOL Min -- 80% VBATT 0 -- Typ 70 Max TBD Unit kohm mA V V mA mA pF - VBATT 20% VBATT TBD TBD IOLT CIn -- -- 3 -- Maximum usable range of the reference voltage supply pin. This range may be modified because of the power supply configuration used in an application. See Table 6, "Power Supply Voltage". 2 Measurement condition for pull resistors: V = V IN SS for pullup and VIN = VDD for pulldown. 6.4 Supply Current Characteristics Table 8. Supply Current Characteristics (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, unless otherwise noted) Characteristics Off current Device is in reset condition (held in reset) and all GPIO at ground. Hibernate current RAM retained (8k, 32k, 64k, or 96k) 2KHz onboard oscillator or 32 kHz crystal oscillator CPU off (stop mode) wake-up from RTI timer, or external request Radio off ADCs not available 8 Kbyte RAM retention 32 Kbyte RAM retention 64 Kbyte RAM retention 96 Kbyte RAM retention Doze current RAM retained (8k, 32k, 64k, or 96k) Onboard 24 MHz oscillator on (high frequency accuracy) CPU off (stop mode) Radio off ADCs available, but inactive 8 Kbyte RAM retention 32 Kbyte RAM retention 64 Kbyte RAM retention 96 Kbyte RAM retention Symbol Min Typ Max Unit A 0.3 1.1 3 5 A A A A 60 65 70 A A A A MC13224V Product Preview, Rev. 1.7 34 Freescale Semiconductor Table 8. Supply Current Characteristics (continued) (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, unless otherwise noted) Characteristics Idle current All RAM active Reference oscillator on (24 MHz) at 1.2 VDC CPU on at 1 MHz Reference clock available to all peripherals Radio off ADCs available, but inactive Run current All RAM active Reference oscillator on (24 MHz) at 1.2 VDC CPU on at reference frequency Radio off Reference clock available to all peripherals ADCs available, but inactive Receive current All RAM active Reference oscillator on (24MHZ) at 1.2 VDC Radio RX on (receiving data) Reference clock available to all peripherals ADC1 available, but inactive CPU on at 2 MHz (DCD) CPU on at 2 MHz (NCD) Transmit current All RAM active Reference oscillator on (24MHZ) at 1.2 VDC Radio TX on (sending data @ 0 dBm) Reference clock available to all peripherals ADCs available, but inactive CPU clock at 2 MHz (< 20% EVM) @ 25 C SPI current - SPI active UART current - UART active SSI current - - SSI active ADC current - ADC active Timer current - timer active I2C current - I2C active Symbol Min Typ Max Unit 750 900 A 3.3 5.0 mA 21 24 24 27 mA 28 - 33 mA mA mA mA mA mA mA MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 35 6.5 RF AC Electrical Characteristics Table 9. Receiver AC Electrical Characteristics for 802.15.4 Modulation Mode (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, fref = 24 MHz, unless otherwise noted.) Characteristic Sensitivity for 1% Packet Error Rate (PER)1 (+25 C, @ package interface; die sensitivity is ~1dB greater) Non-coherent Differential Chip Detection (DCD) Non-coherent Detection (NCD) Saturation (maximum input level) Channel Rejection for 1% PER (desired signal -82 dBm) +5 MHz (adjacent channel) -5 MHz (adjacent channel) +10 MHz (alternate channel) -10 MHz (alternate channel) >= 15 MHz Frequency Error Tolerance Symbol Rate Error Tolerance 1 Symbol Min Typ Max Unit SENSmax - -96 -100 10 40 40 57 57 65 120 -91 -95 35 35 50 50 60 200 80 dBm dBm dB kHz ppm The digital modem contains a block designated as the RX Modem. The Rx Modem can operate in: 1) Non-coherent Differential Chip Detection (DCD) mode which has 3-4dBm less sensitivity but requires 3-4mA less receiver current, and 2) Non-coherent Detection (NCD) mode which has 3-4dBm greater sensitivity but requires 3-4mA greater receiver current. Table 10. Transmitter AC Electrical Characteristics for 802.15.4 Modulation Mode (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, fref = 24 MHz, unless otherwise noted.) Characteristic Nominal Output Power1 Maximum Output Power2 (EVM < 20%) Symbol Pout Min - Typ 0 +5 7 12 16 35 250 -55 -64 50 Max - Unit dBm dBm % Error Vector Magnitude Pout @ -30 dBm Pout @ 0 dBm Pout @ +4 dBm Output Power Control Range Over the Air Data Rate 2nd Harmonic3 EVM - - dB kbps dBm/MHz dBm/MHz dB dB ohm 3rd Harmonic3 Spurious Emissions 30-1000 MHz 1-12.75GHz Nominal Impedance (RF_RX_TX) 1 2 Register sets output power to nominal (0 dBm typical). Register sets output power to maximum. 3 Measurements taken at output of evaluation circuit set for maximum power out and averaged over 100ms. MC13224V Product Preview, Rev. 1.7 36 Freescale Semiconductor 6.6 Crystal Reference Clock Oscillator Characteristics MC13224V REFERENCE OSCILLATOR Course Tune[4] 4pF Course Tune[4] 4pF Course Tune[3:0] 8pF 4pF 2pF 1pF 1 MEG (nom) 8pF 4pF Course Tune[3:0] 2pF 1pF Fine Tune[4:0] 0-5pF with steps of 160 fF. OSC_IN Fine Tune[4:0] 0-5pF with steps of 160 fF. OSC_OUT Y1 CRYSTAL Cstray Cstray Figure 10. Reference Oscillator Model Table 11. Reference Oscillator Specifications Characteristic Crystal frequency Oscillator frequency tolerance @ 25 C Oscillator frequency tolerance over temperature range. 802.15.4 mode Equivalent series resistance External load capacitance Internal Osc startup time (13 MHz - 26 1 Symbol Min 13 Typ 24 Max 26 20 Unit MHz ppm +/- 40 ESR CLext 60 None required (onboard) 0.8 1.2 ppm pF ms MHz)1 This is part of device wake-up time. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 37 6.7 Optional 32.768 KHz Crystal Oscillator Specifications MC13224V 32.768 kHz OSCILLATOR Feedback OSC_IN OSC_OUT Y1 CRYSTAL Cstray1 CL1 CL2 Cstray2 Figure 11. 32.768 KHz Oscillator Model Table 12. 32.768 Oscillator Specifications Characteristic Crystal frequency1 Frequency tolerance @ 25 C Frequency tolerance over temperature2 Load capacitance Equivalent series resistance (ESR) Shunt capacitance Tolerated drive level 1 2 Symbol Min Typ 32.768 20 Max Unit KHz ppm ppm pF k pF W -0.034 0.006ppm / (25-T)2 11 12.5 13 60 1.35 1 Recommended crystal Abracom Corporation crystal part number Example; Stability at -20xC is: -0.034 x (25-[-20])2= -68.8ppm. ABS25-32.768-12.5-B MC13224V Product Preview, Rev. 1.7 38 Freescale Semiconductor 6.8 Internal Low Speed Reference Oscillator Specifications Table 13. Internal 2 KHz Oscillator Specifications Characteristic Oscillator frequency tolerance over temperature Frequency tolerance @ 25 C Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient Initial calibration time Symbol Min Typ 2 2 - Max - Unit KHz KHz % %/C %/V ms 6.9 Control Timing and CPU Bus Specifications Table 14. MCU Control Timing (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, fref = 24 MHz, unless otherwise noted.) Parameter CPU Bus frequency (tcyc = 1/fBus) CPU Bus frequency with active TX or RX Real-time interrupt internal oscillator frequency External reset pulse width2 Symbol fBus Min fref/64 1 2 Typical -- Max fref 1 Unit MHz MHz 2 4 -- -- KHz osc clks ns External minimum interrupt pulse width (KBI[7:4]) 1 2 Normal operation uses a 24 MHz reference. The MC13224V allows up to a 26 MHz max reference oscillator. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. There always must be 3 clocks of the operating oscillator; this can vary from the low power oscillators to the reference oscillator. 6.9.1 Timer Module Input Characteristics Four-bit synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the peripheral clock rate. Table 15 shows timer input timing values. Table 15. Timer Input Timing (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, fref = 24 MHz, unless otherwise noted.) Parameter External clock frequency External clock period Input capture pulse width Symbol Min dc >3 TBD Max peripheral_bus_clk/3 -- -- Unit MHz tcyc tcyc MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 39 6.10 SPI Timing tCYC SPI_SCK SPI_SS (slave in) tSS_SU tXX_SU tXX_H tMO,tSO tSS_H SPI_MOSI (slave in) SPI_MISO (master in) SPI_MOSI (master out) SPI_MISO (slave out) Figure 12. SPI Timing Diagram Table 16 describes the timing requirements for the SPI system. Table 16. SPI Timing Parameter Master SPI_SCK Period Slave SPI_SCK Period Slave SPI_SS Setup Time Slave SPI_SS Hold Time Slave SPI_MOSI Setup Time Slave SPI_MOSI Hold Time Master SPI_MISO Setup Time Master SPI_MISO Hold Time Master SPI_MOSI Output Time Slave SPI_MISO Output Time (with 15 pf load) Symbol Min peripheral_ bus_clk*2 10 10 10 10 10 20 0 Typical 38 Max peripheral_ bus_clk * 256 Unit ns ns ns ns ns ns ns ns tCYC tCYC tSS_SU tSS_H tSI_SU tSI_H tMI_SU tMI_H tMO tSO 5 20 ns ns MC13224V Product Preview, Rev. 1.7 40 Freescale Semiconductor 6.11 6.12 SSI Timing I2C Specifications Table 17 describes the timing requirements for the I2C system. The I2C module is driven by the peripheral bus clock (typically max 24 MHz) and the SCL bit clock is generated from a prescaler. The prescaler divide ratio can be programmed from 61,440 to 160 (decimal) which gives a maximum bit clock of 150 kbps. Table 17. I2C Signal DC Specifications (I2C_SDA and I2C_SCL) Parameter Input Low Voltage Input High Voltage Input hysteresis Output Low Voltage1 (IOL = 5 mA) Symbol VIL VIH Vhys VOL IIN Cin Min -0.3 0.7 VBATT 0.06 x VBATT 0 - Typical - Max 0.3 VDDINT VBATT + 0.3 -- Unit V V V V A pF mA mA - 0.2 VBATT 1 <10 Input Current (VIN = 0 V or VDDINT) Pin capacitance Maximum current in/out per port pin Maximum total IOL for all port pins 1 -- IOLT -- TBD TBD SDA and SCL are open drain outputs SDA tf tr tSU;DAT tHD:STA tr tBUF tLOW SCL tf tHD tHD;DAT S tHIGH Sr P S tSU;STA tSU;STO Figure 13. I C Timing Diagram 2 NOTE The C timing limits reflect values that are necessary meet to the I2C Bus specification. I2 MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 41 Table 18. I2C Signal AC Specifications1 Parameter Symbol Standard-Mode Min SCL clock frequency (when source) Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data setup time Rise time for both SDA and SCL signals Fall time for both SDA and SCL signals Bus free time between a STOP and START condition Capacitive load for each bus line 1 2 Fast-Mode Min 0 0.6 1.3 0.6 0.6 02 1004 20 + 0.1Cb5 20 + 0.1Cb5 Unit Max 100 3.453 1000 300 400 Max 150 0.93 300 300 400 kHz s s s s s ns ns ns s pF fSCL tHD;STA tLOW tHIGH tSU;STA tSHD;DAT tSU:DAT tr tf tBUF Cb 0 4.0 4.7 4.0 4.7 02 250 4.7 - 1.3 - All values referred to VIHmin and VILmax levels A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3 The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t SU;DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. 5 C = total capacitance of one bus line in pF. If mixed with Hs-mode devices, the faster fall-times are allowed. b MC13224V Product Preview, Rev. 1.7 42 Freescale Semiconductor 6.13 FLASH Specifications Table 19. FLASH Characteristics (TA = 25 C, fref = 24 MHz, unless otherwise noted.) Characteristic Supply voltage for program/erase/read (with directly regulated supply) SPI clock frequency Read current (13 MHz) Program and erase current Standby current Sector erase duration Block erase duration Chip erase duration Byte program duration Program/erase endurance Data retention Symbol Vprog/erase fFCLK Min 1.70 Typical Max 1.90 13 Unit V MHz mA mA A ms ms ms s cycles 9 10 2 15 15 10 75 75 150 60 100,000 tD_ret 100 -- years 6.14 ADC Characteristics Table 20. ADC Electrical Characteristics (Operating) (VBATT, LREG_BK_FB = 3.3 V, TA = 25 C, fref = 24 MHz, unless otherwise noted.) Characteristic Condition Enabled Symbol Min -- -- Typical 2.65 5 -- -- -- 1.2 Max - Unit mA A ADC supply current (per ADC) Reference potential, low Reference potential, high Analog input voltage1 "Battery" input channel reference voltage 1 Disabled VREFL VREFH VINDC VSS VREFL VSS - 0.2 VREFH VBATT VDD +0.2 V V V V Maximum electrical operating range, not valid conversion range. Table 21. ADC Timing/Performance Characteristics Characteristic Resolution Effective Resolution 10.5 Symbol Condition Min Typ Max 12 Unit Bits Bits MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 43 Table 21. ADC Timing/Performance Characteristics (continued) Characteristic Number of input channels ADC conversion clock frequency Conversion cycles (continuous convert) Conversion time Input Leakage Current Analog Input Voltage1 1 Symbol Condition Min Typ Max 8 Unit fADCCLK CCP Tconv - 6 -- 50 KHz ADCCLK cycles 20 VREFH s nA V -- VAIN VDD VREFL -- Analog input must be between VREFL + 0.2 and VREFH - 0.2 for valid conversion. 7 7.1 Developer Environment Hardware Development Interfaces The MC1322x family is supported by a full set of hardware/software evaluation and development tools. The ARM debug environment supports both a JTAG debug interface and an extended capability Nexus interface. 7.1.1 JTAG Hardware Debug Port The JTAG port is the simpler and more common debug port for the ARM core. A standard 20-pin connector as described in Section 5.2.1, "ARM JTAG Interface Connector"", is connected to the TDI, TMS, TCK, TDO, and RTCK signals of the MC13224V. Through the JTAG serial interface, standard debug and development activities such as accessing memory and registers, control of the CPU, download of FLASH memory, and software debug can be accomplished. 7.1.2 A7S Nexus3 (NEX) ARM7 Core Development Interface The development and debug environment of the ARM7TDMI-S core is based on the A7S Nexus3 interface (compliant with a Class 3 device of the IEEE-ISTO 5001 standard for real-time embedded system design). This interface allows expansion of the development features of the JTAG port (through the addition of auxiliary signals, see Section 5.2.2, "Nexus Mictor Interface Connector"). Development features include: * Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus static code may be traced. * Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to (selected) internal memory resources. * Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace MC13224V Product Preview, Rev. 1.7 44 Freescale Semiconductor * * * * * * * Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. Run-time access to the memory map via the JTAG port. This allows for enhanced download/upload capabilities Watchpoint Messaging (WPM) via the auxiliary pins Watchpoint Trigger enable of Program and/or Data Trace Messaging Auxiliary interface for higher data input/output Registers for Program Trace, Ownership Trace, Watchpoint Trigger, and Read/Write Access Programmable processor stall function to mitigate message queue overrun risk All features controllable and configurable via the JTAG port 7.2 Software Development Tools An Integrated Development Environment (IDE) is available to facilitate the development of embedded applications targeting the MC13224V platform. Features of the IDE include: * Project management tools and code editor * Highly optimizing ARM compiler supporting C and C++ * Extensive JTAG and RDI debugger support * Run-time libraries including source code * Relocating ARM assembler * Linker and librarian tools * Debugger with ARM simulator, JTAG support and support for RTOS-aware debugging on hardware * RTOS plug-ins available * Code templates for commonly used code constructs * Sample projects for evaluation boards * User and reference guides, both printed and in PDF format * Context-sensitive online help The IDE is complemented by the BeeKitTM Wireless Connectivity Toolkit. BeeKit is a stand alone software application targeting Windows(R) operating systems. BeeKit provides a graphical user interface (GUI) in which users can create, modify, save, and update wireless networking solutions. With the solution explorer property list windows, users can set configuration parameters to control the setup and execution behavior of the wireless link within their application. The configuration parameters can be validated inside BeeKit to ensure all values provided are within acceptable ranges prior to generation of a workspace. All this functionality provides a mechanism for developers to configure and validate their network parameters without having to navigate through multiple source files to configure the same parameters. BeeKit supports Freescale's Simple MAC (SMAC), IEEE 802.15.4-compliant MAC, and the Freescale BeeStackTM. MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 45 7.3 Development Hardware Several different development modules and kits will be available to allow evaluation of ZigBee and IEEE 802.15.4 applications. The modules will provide capabilities for Coordinator, Router, and End Device nodes. Reference designs will be available for RF design and low power applications including 2-layer and 4-layer PCBs. 8 Preliminary Mechanical Diagrams (Case 1901-01, non-JEDEC) Figure 14. Mechanical Diagram (1 of 2) MC13224V Product Preview, Rev. 1.7 46 Freescale Semiconductor Figure 15. Mechanical Diagram Bottom View (2 of 2) MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 47 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM7TDMI-S is the trademark of ARM Limited.(c) Freescale Semiconductor, Inc. 2005, 2006, 2007, 2008 Document Number: MC1322x Rev. 1.7 06/2008 |
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